ヤマウチ　ヒロシ   Yamauchi Hiroshi   山内　博    所属   千葉工業大学  工学部 宇宙・半導体工学科    職種   准教授
言語種別	英語
発行・発表の年月	2014/04
形態種別	学術雑誌
査読	査読あり
標題	Fabrication of stacked logic circuits for printed integrated circuits
執筆形態	共著
掲載誌名	Jpn. J. Appl. Phys.
掲載区分	国内
出版社・発行元	Japan Society of Applied Physics
巻・号・頁	53(5)
著者・共著者	K.Kudo,I.Kodera,R.Aino,H.Yamauchi,S.Kuniyoshi,M.Sakai
概要	We have demonstrated NAND and NOR logic circuit operations of stacked-structure complementary thin-film transistors (TFTs) using 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and soluble ZnO as active layers. Bottom-gate-type TIPS-pentacene TFTs, as p-channel transistors, were formed on n-channel ZnO TFTs with common gate electrodes. Solution-processed silicone-resin layers were used as gate dielectric and electrical interconnection layers between lower and upper TFTs. The stacked-structure integrated circuits have several advantages such as ease of active layer formation, compact device area per stage, and the short length of the interconnection compared with the planar configuration in a conventional logic circuit. © 2014 The Japan Society of Applied Physics.
DOI	10.7567/JJAP.53.05HB08
ISSN	1347-4065