ヤマウチ　ヒロシ   Yamauchi Hiroshi   山内　博    所属   千葉工業大学  工学部 宇宙・半導体工学科    職種   准教授
言語種別	英語
発行・発表の年月	2011/02
形態種別	学術雑誌
査読	査読あり
標題	CMOS Circuits Based on a Stacked Structure Using Silicone-Resin as Dielectric Layers
執筆形態	共著
掲載誌名	IEICE Trans. Electron.
掲載区分	国内
出版社・発行元	IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
巻・号・頁	E94-C(2),pp.136-140
著者・共著者	K. Kikuchi,F. Pu,H. Yamauchi,M. Iizuka,M. Nakamura and K. Kudo
概要	We have demonstrated the inverter operation of stacked-structure CMOS devices using pentacene and ZnO as active layers. The fabrication process of the device is as follows: A top-gate-type ZnO thin-film transistor (TFT). working as an n-channel transistor, was formed on a glass substrate. Then, a bottom-gate-type pentacene TFT, as a p-channel transistor, was fabricated on top of the ZnO TFT while sharing a common gate electrode. For both TFTs, solution-processed silicone-resin layers were used as gate dielectrics. The stacked-structure CMOS has several advantages, for example, easy patterning of active material, compact device area per stage and short interconnection length, as compared with the planar configuration in a conventional CMOS circuit.
DOI	10.1587/transele.E94.C.136
ISSN	1745-1353