オオニシ　タカユキ   Takayuki Onishi   大西　隆之    所属   千葉工業大学  情報変革科学部 情報工学科    職種   教授
発行・発表の年月	2020/03
形態種別	学術雑誌
査読	査読あり
標題	Low delay 4K 120fps HEVC decoder with parallel processing architecture
執筆形態	共著
掲載誌名	IEICE Transactions on Electronics
掲載区分	国内
出版社・発行元	The Institute of Electronics, Information and Communication Engineers
巻・号・頁	103(3),77-84頁
著者・共著者	Nakamura, Ken,Kobayashi, Daisuke,Omori, Yuya,Osawa, Tatsuya,Onishi, Takayuki,Nitta, Koyo,Iwasaki, Hiroe
概要	In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.
DOI	10.1587/transele.2019LHP0005
ISSN	0916-8524/1745-1353