オオニシ　タカユキ   Takayuki Onishi   大西　隆之    所属   千葉工業大学  情報変革科学部 情報工学科    職種   教授
発行・発表の年月	2019
形態種別	国際会議プロシーディングス
査読	査読あり
標題	A low power motion estimation engine with adaptive bit-shifted SAD calculation
執筆形態	共著
掲載誌名	Proceedings - IEEE International Symposium on Circuits and Systems
掲載区分	国外
巻・号・頁	2019-May
担当区分	筆頭著者
著者・共著者	Takayuki Onishi,Yuya Omori,Ken Nakamura,Hiroe Iwasaki,Atsushi Shimizu
概要	This paper describes a motion estimation (ME) engine that achieves both power efficiency and coding quality for real-time ultra-high definition video encoders. Sum of absolute difference (SAD) calculations are performed with bit-shortened SAD engines to reduce power, and bit extraction positions are adaptively shifted in accordance with the flatness of picture luminance values to maintain calculation precision. Power simulations with a High Efficiency Video Coding encoder LSI design [2] show that the ME engine reduces power consumption by 18-39% with 4-bit shortened SAD calculation, while coding efficiency loss is suppressed by up to 57% with adaptive bit-shifting. The ME engine is especially effective for high dynamic range pictures with downscaled luminance values, which are suitable for today's 4K and 8K video contents.
DOI	10.1109/ISCAS.2019.8702287
ISSN	0271-4310