Faculty Information - Takayuki Onishi

Office

Academic background

Present specialized field

Works

（Last updated : 2025-09-04 14:41:27）

Takayuki Onishi
Department of Computer Science, Faculty of Innovative Information Science

Professor

■ Office

Tsudanuma Campus, No.1 Building,9th floor room 020909

■ Academic background

1.	2010/10～2016/09	, Doctor of Philosophy in Engineering
2.	1997/04～1999/03	〔Master Course〕 Department of Electrical Engineering and Information Systems, Graduate School, Division of Engineering, The University of Tokyo, Completed,
3.	1993/04～1997/03	Department of Information and Communication Engineering, Faculty of Engineering, The University of Tokyo, Graduated,

■ Present specialized field

Computer system, High performance computing

■ Works

1.	Article	A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming IEICE TRANSACTIONS on Information and Systems pp.46-57 (Collaboration) 2023
2.	Article	4K 120fps HEVC encoder with multi-chip configuration IEICE Transactions on Communications pp.749-759 (Collaboration) 2021
3.	Article	Low delay 4K 120fps HEVC decoder with parallel processing architecture IEICE Transactions on Electronics pp.77-84 (Collaboration) 2020/03
4.	Article	4K 120fps HEVC temporal scalable encoder with super low delay 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 pp.410-413 (Collaboration) 2019/11
5.	Article	Image Pre-Transformation for Recognition-Aware Image Compression Proceedings - International Conference on Image Processing, ICIP pp.2686-2690 (Collaboration) 2019/09
6.	Article	A low power motion estimation engine with adaptive bit-shifted SAD calculation Proceedings - IEEE International Symposium on Circuits and Systems (Collaboration) 2019
7.	Article	A real-time 4K HEVC multi-channel encoding system with content-aware bitrate control Proceedings - IEEE Global Communications Conference, GLOBECOM (Collaboration) 2019
8.	Article	An MMT Module for 4K/120fps temporally scalable video Proceedings - IEEE International Symposium on Circuits and Systems (Collaboration) 2019
9.	Article	An HEVC real-time encoding system with high quality HDR color representations 2018 IEEE International Conference on Consumer Electronics, ICCE 2018 pp.1-2 (Collaboration) 2018/03/26
10.	Article	A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K IEEE Transactions on Multi-Scale Computing Systems pp.491-499 (Collaboration) 2018
11.	Article	A 4K/60p HEVC real-time encoding system with high quality HDR color representations IEEE Transactions on Consumer Electronics pp.433-441 (Collaboration) 2018
12.	Article	A single-chip 4K 60-fps 4: 2: 2 HEVC video encoder LSI employing efficient motion estimation and mode decision framework with scalability to 8K IEEE Transactions on Very Large Scale Integration (VLSI) Systems pp.1930-1938 (Collaboration) 2018
13.	Article	A 120 fps High Frame Rate Real-time Video Encoder NTT Technical Review pp.13-17 (Collaboration) 2017
14.	Article	Professional H.264/AVC CODEC chip-set for high-quality HDTV broadcast infrastructure and high-end flexible CODEC systems 2007 IEEE Hot Chips 19 Symposium, HCS 2007 (Collaboration) 2016/05/31
15.	Article	Single-chip 4K 60fps 4:2:2 HEVC video encoder LSI with 8K scalability IEEE Symposium on VLSI Circuits, Digest of Technical Papers pp.C54-C55 (Collaboration) 2015/08/31
16.	Article	Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure 2015 IEEE Hot Chips 27 Symposium, HCS 2015 (Collaboration) 2015/05/23
17.	Article	An H. 264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures IEICE transactions on electronics pp.432-440 (Collaboration) 2012
18.	Article	MVC real-time video encoder for full-HDTV 3D video Digest of Technical Papers - IEEE International Conference on Consumer Electronics pp.166-167 (Collaboration) 2012
19.	Article	A distributed stream multiplexing architecture for multi-chip configuration beyond HDTV IEICE TRANSACTIONS on Information and Systems pp.2862-2867 (Collaboration) 2008
20.	Article	An H.264/AVC high422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures IEEE Symposium on VLSI Circuits, Digest of Technical Papers pp.106-107 (Collaboration) 2008
21.	Article	Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4:2:2 H.264/AVC encoder LSI Proceedings - IEEE International Symposium on Circuits and Systems pp.800-803 (Collaboration) 2008
22.	Article	Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level IEEE Transactions on Very Large Scale Integration (VLSI) Systems pp.1055-1059 (Collaboration) 2007/09
23.	Article	Highly accurate de-jittering scheme for broadcast quality video transmission Systems and Computers in Japan pp.81-88 (Collaboration) 2006
24.	Article	New set-top box for interactive visual communication of home entertainment using mpeg-2 full-duplex codec lsi IEEE Transactions on Consumer Electronics pp.640-641 (Collaboration) 2005
25.	Article	A distributed TS-MUX architecure for multi-chip extension beyond the HDTV level Proceedings - IEEE International Symposium on Circuits and Systems (Collaboration) 2004
26.	Article	A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems Proceedings of the Custom Integrated Circuits Conference pp.177-180 (Collaboration) 2003
27.	Article	Single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level Proceedings -Design, Automation and Test in Europe, DATE pp.2-7 (Collaboration) 2003
28.	Article	VASA: Single-chip MPEG-2 422P@ HL CODEC LSI with Multi-chip Configuration for Large Scale Processing beyond HDTV Level IEEE Hot Chips pp.2002-8 (Collaboration) 2002
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